![]() As Q4 goes into saturation, the output voltage Y will be pulled down to low. As Q2 conducts, the voltage at X will drop down and Q3 will be OFF, whereas the voltage at Z will increase to turn ON Q4. Therefore D3 is forward biased and base current is supplied to transistor Q2 via R1 and D3. 3 Total: 25 marks The schematic diagram of a TTL logic gate is given below where Vcc 5V and each transistor is a 3C2BJT1 (datasheet attached). A and B both high: If both A and B are connected to then both diodes D1 and D2 will be reverse biased and do not conduct.As Q3 acts as an emitter follower, output Y will be pulled to Vcc. This voltage acts as a base voltage for Q3. So the collector voltage of Q2 will be equal to Vcc. This voltage is insufficient to turn on Q2 so it remains OFF. ![]() Either A or B low: If anyone input is connected to ground with other left open or connected to Vcc the corresponding diode (D1 or D2) will conduct.As Q3 is operating in emitter follower mode, output Y will be pulled up to high voltage Y= 1 Therefore its collector voltage rises to Vcc. Join ResearchGate to find the people and research you need to help your work. See below for more detailed instructions. ![]() Drag from the hollow circles to the solid circles to make connections. Select gates from the dropdown list and click 'add node' to add more gates. Investigate the behaviour of AND, OR, NOT, NAND, NOR and XOR gates. This voltage is insufficient to forward bias B-E junction of Q2. Download scientific diagram Diagram of Transistor-Transistor Logic (TTL). A free, simple, online logic gate simulator. Hence D1 and D2 will conduct to force the voltage at point C to 0.7V.
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